Highlights:

  • In TSMC’s 1.6-nanometer technology, the power delivery wires are directly connected to the source and drain.
  • According to TSMC, a 1.6-nanometer chip can use the same amount of energy to reach clock rates up to 10% faster than those of a previous-generation product.

TSMC’s new chipmaking process will enable developing quicker and efficient data center processors.

The new technology by Taiwan Semiconductor Manufacturing Co. Ltd., termed TSMC’s 1.6-nanometer process, was recently unveiled at a corporate function in Santa Clara, California. Executives also gave an overview of NanoFlex, a second future chipmaking technique. Customers can swap out different kinds of transistors for one CPU.

The transistors in a modern chip are housed behind a web of tiny wires that serve three purposes. To make calculations easier, the cables carry data between the transistors and deliver electricity to them. They also send out the clock signal, a type of cue that the processor sends out at predetermined intervals to maintain circuit synchronization.

The 1.6-nanometer node from TSMC approaches chip wiring differently. The cables that supply power to transistors in processors manufactured using this technique will be positioned below the transistors instead of above. Backside power delivery is the term for this configuration, which makes it easier to produce chips with higher efficiency.

Mitigating a technical problem called IR drop is one way the technique boosts processor performance. This occurrence causes a chip’s transistors to receive less voltage, slowing the chip’s operation. According to TSMC, such voltage drops in the wires are less likely within its 1.6-nanometer node.

Rival Intel Corp. is also using backside power delivery in its 20A process, also referred to as the business’s five-nanometer node. The company claims that using this technique may streamline power distribution, and a chip’s circuitry can be arranged closer together. As a result, adding more transistors can increase a processor’s computing power.

The four primary parts of a transistor are the source, drain, channel, and gate. The drain is the transistor’s outflow, whereas the source is the point of entrance for electricity. The channel and gate are accountable for coordinating the flow of electrons.

In TSMC’s 1.6-nanometer technology, the power delivery wires are directly connected to the source and drain. The company claims that compared to alternative backside power delivery methods, such as the one used by Intel, the manufacturing of that design is more complex. According to TSMC, choosing a more intricate design will increase the chips’ efficiency for clients.

According to the business, chips produced using its 1.6-nanometer process will use 15% to 20% less energy than silicon produced using earlier technology. Customers might also sacrifice some power efficiency in exchange for better performance. According to TSMC, a 1.6-nanometer chip can use the same amount of energy to reach clock rates that are up to ten percent faster than those of a previous-generation product.

Executives from the chipmaker also provided details on NanoFlex, a forthcoming technology, during the event when the company unveiled its 1.6-nanometer node. It makes it possible to design semiconductors that combine various transistor types in diverse layouts for power efficiency, speed, and size. Customers may be able to precisely match the specifications of their projects with TSMC-made chips due to this flexibility.

The company’s two-nanometer node, which is slated to go into mass production the following year, will mark the debut of NanoFlex. For its part, the 1.6-nanometer process is scheduled to go online in the second part of 2026. Both nodes use the gate-all-around transistor architecture from TSMC.